The present invention relates to semiconductor device testers.
This application is related to Korean Application No. 98-53644, filed Dec. 8, 1998, the disclosure of which is hereby incorporated herein by reference.
Various complex semiconductor devices, such as integrated circuit packages with a number of input/output pins, are commonly manufactured and utilized in a variety of areas. It is often desirable to test such devices after their manufacture to verify their performance. To facilitate testing of such integrated semiconductor devices a variety of semiconductor device tester designs have been provided. Such conventional testers typically provide for detecting transitions of output data at a specific pin during a test of a semiconductor device and further to detect a data output speed or rate for a specific pin. Generally, however, such conventional testers do not provide for a measurement of comparative data streams between different input/output pins of the semiconductor device. Accordingly, such devices typically are not able to measure the skew, or response time difference, between data output from respective data input/output pins of a semiconductor device. This limitation is becoming problematic as semiconductor device designers work to reduce such skew in light of the ever increasing speed of operations of various semiconductor devices. As the semiconductor devices migrate to ever higher operating speeds, the likelihood of errors being generated as a result of skew between output data increases.
One type of prior art semiconductor tester device attempts to use a data strobe in the semiconductor device tester. Nonetheless, a problem may still exist using this approach in that expected values generated by the tester and the actual output data from the semiconductor device being tested are generally compared only to detect transitions of output data at a point and time specified by the strobe which is not suitable for determining the skew between the output of two data input/output pins of the semiconductor device.
An example of such a prior are semiconductor device tester will now be further described with reference to the schematic block diagram of FIG.1. As shown in FIG.1, the semiconductor device 100 is electrically coupled to a tester 200. The semiconductor device 100 includes control signal input pins and data input/output pins which are coupled to the tester 200. The tester 200 includes a control signal input driver 10, data input drivers 12-1, 12-2, . . . , 12-n, amplifier gates 14-1, 14-2, . . . , 14-n, 16-1, 16-2, . . . , 16-n, inverters 18-1, 18-2, . . . , 18-n, AND gates 20-1, 20-2, . . . , 20-n, 22-1, 22-2, . . . , 22-n, 26-1, 26-2, . . . , 26-n, OR gates 241, 242, . . . , 24-n, D flip flops 28-1, 28-2, . . . , 28-n, a test pattern generator circuit 30 and a timing generator circuit 32.
The embodiment illustrated in FIG.1 represents a tester for use where the data input/output pins of the semiconductor device 100 are common. When the data input and data output pins of the semiconductor device 100 are separate pins, it is to be understood by those of ordinary skill in the art that the data input drivers are connected to data input pins 12 while the amplifier gates 14 are connected to data output pins.
Operations of the prior art semiconductor device tester will now be further described with reference to FIG.1. The tester 200 sends a control signal CON to a control signal input pin of the semiconductor device 100 through the control signal input driver amplifier 10 and further sends the control signal CON to the test pattern generator 30. The test pattern reference data output from the test pattern generator 30 is then input to the semiconductor device 100 via the data input drivers 12-1, 12-2, . . . , 12-n connected to respective data input/output pins of the semiconductor device 100. The semiconductor device 100 further outputs data corresponding to the input reference data test pattern on receipt of a control signal from the input driver 10 while the test pattern generator 30 outputs the reference data (or expected values). The respective amplifier gates 14-1, 14-2, . . . , 14-n in turn generate active signals when the voltage which is output through the corresponding input/output pins is higher than the high reference voltage (VOH). The amplifier gates 16-1, 16-2, . . . , 16-n respectively generate active signals when voltages output through the corresponding input/output pins are lower than the low voltage reference signal (VOL).
As used for purposes of the description herein an xe2x80x9cactivexe2x80x9d state will be used interchangeably with a xe2x80x9chighxe2x80x9d or xe2x80x9csetxe2x80x9d state. Similarly, an xe2x80x9cinactivexe2x80x9d state will be used interchangeably with a xe2x80x9clowxe2x80x9d or xe2x80x9cresetxe2x80x9d state. However, it is to be understood that the present invention may equally be applied in circuits using what is commonly referred to as negative or inverse logic with the necessary changes to embodiments described herein being readily known to those of ordinary skill in the art.
As can be seen from the schematic block diagram of FIG.1, the AND gates 20-1, 20-2, . . . , 20-n respectively perform logical multiplications of the output signals of the corresponding amplifier gates 141, 14-2, . . . , 14-n and non-inverted levels output from the test pattern generator 30, thereby generating high (active) signals when both inputs are at high levels. Similarly, the AND gates 22-1, 22-2, . . . , 22-n respectively perform logical multiplications on output signals from corresponding amplifier gates 16-1, 16-2, . . . , 16-n and signals from the test pattern generator 30 inverted by the inverters 18-1, 18-22, . . . , 18-n to thereby generate high level output signals when the signal from the test pattern generator 30 and the respective output pin of the semiconductor device 100 are both at a low level. Accordingly, the AND gates 20-1, 20-2, . . . , 20-n detect values of high levels output from corresponding data input/output pins of the semiconductor device 100 while the AND gates 22-1, 22-2, . . . , 22-n respectively detect values of low levels output from associated ones of the data input/output pins of the semiconductor device 100. As a result, the OR gates 24-1, 24-2, 24-n respectively generate high level signals when matched values of high levels are detected by the AND gates 20-1, 20-2, . . . , 20-n and when low level values are detected by the AND gates 22-1, 22-2, . . . , 22-n.
When the output signal of the OR gates 24-1, 24-2, . . . , 24n are at low levels, they are judged to be inferior and at high levels, they are judged to be normal. The AND gates 26-1, 26-2, . . . , 26-n, in turn, respectively perform logical multiplications on the signals COM EN generated by the test pattern generator 30 and the output signals from the OR gates 24-1, 24-2, . . . , 24-n to thereby generate a high or low level signal output. Finally, the D flip flops 28-1, 28-2, . . . , 28-n, responsive to strobe signals generated by the timing generator circuit 32, generate output signals of the AND gates 26-1, 26-2, . . . , 26-n as the output signals OUT 1, OUT 2, . . . , OUT n respectively. In other words, the tester 200 generates output signals for the respective corresponding input/output pins of the semiconductor device 100 with reference to the high and low level voltage reference values VOH, VOL respectively at times defined by the strobe signal to discriminate whether there has been a state transition on the input/output pins at the time of the strobe signal.
This prior art semiconductor device tester design has various problems. The tester only determines whether there has been a transition of output data at a strobe signal controlled time interval. The tester does not provide for measurements of relative transition times (or skew) between two different input/output lines of the semiconductor device 100. Accordingly, there is a need for improved semiconductor device testers.
It is, therefore, an object of the present invention to provide semiconductor device testers that may measure skew between output pins of a semiconductor device.
In order to provide for the foregoing and other objectives, semiconductor device testers are provided which measure skew between two or more output pins of a semiconductor device independent of a strobe timing input. More particularly, a skew signal is generated by a comparator circuit that changes state when the respective outputs transition state, for example, from matching to differing states. In a two output pin embodiment, for instance, when one of the output pin changes state before the other and both initially are in the same state, a flip flop is set at the time when the data on the output pins first differs, i.e. when the first output pin transitions to a new state. The flip flop is then reset when the second output pin subsequently transitions to the new state and again matches the first output pin. The resulting duration of the output of the flip flop thereby corresponds to the time of skew of the output pins regardless of the initial state of the pins although the relevant duration may be during either one of the active or inactive state depending on whether the state of the two output pins initially matches or differs.
In one embodiment of the present invention, a semiconductor device tester is provided having an interface that couples the semiconductor device tester to a plurality of output pins of a semiconductor device. A comparator circuit electrically couples to at least two of the plurality of output pins of the semiconductor device and generates a skew signal having a duration corresponding to a time period when data on the at least two of the plurality of output pins differs. A timing circuit may be electrically coupled to the skew signal that measures the duration of the skew signal. The comparator circuit includes a first circuit that generates an active signal when the data on the at least two of the plurality of output pins differs and an inactive signal when the data on the at least two of the plurality of output pins matches. The comparator circuit further includes a second circuit that generates an active signal when the data on the at least two of the plurality of output pins matches and an inactive signal when the data on the at least two of the plurality of output pins differs. A flip flop has a set input electrically coupled to the first circuit and a reset input electrically coupled to the second circuit and outputs the skew signal.
A plurality of comparator circuits may be included in the tester each having as inputs at least two of the output pins of the semiconductor device. The flip flops may be SR flip flops. The first circuit may be a logical exclusive OR circuit and the second circuit may be a logical exclusive NOR circuit.
In another embodiment, the logical exclusive OR circuit includes at least a selected number of exclusive OR gates, the selected number of exclusive OR gates being selected based on a number of the at least two of the plurality of output pins. The logical exclusive NOR circuit includes at least a selected number of exclusive NOR gates, the selected number of exclusive NOR gates being the same as the selected number of exclusive OR gates. The number of the at least two of the plurality of output pins may be three and the selected number of exclusive OR gates may be two.
In a further embodiment of the present invention, the semiconductor device tester includes a control signal input driver circuit electrically coupled to the semiconductor device. A test pattern generator circuit generates reference data responsive to the control signal input driver circuit. A timing generator circuit generates a strobe. A signal detection circuit electrically coupled to the test pattern generator circuit and the at least two of the plurality of output pins of the semiconductor device detects when a transition has occurred on one of the at least two of the plurality of output pins responsive to the strobe.
In another embodiment of the present invention, the timing circuit is configured to measure a time between a first edge of the skew signal and a second edge of the skew signal. The timing circuit may be configured to measure a time from an enable signal input to the first flip flop to a disable signal input to the first flip flop and to measure a time from an enable signal input to the second flip flop to a disable signal input to the second flip flop.
In yet another embodiment of the present invention, a semiconductor device tester is provided that includes a predetermined number of first circuits that generate an active signal when data on selected ones of a plurality of output pins of a semiconductor device differs and an inactive signal when the data on the selected ones of the plurality of output pins matches. A predetermined number of second circuits, each of the second circuits being associated with one of the first circuits, generate an active signal when the data on the selected ones of the plurality of output pins matches and an inactive signal when the data on the selected ones of the plurality of output pins differs. A predetermined number of flip flops, each of the flip flops having a set input electrically coupled to an associated one of the first circuits and a reset input electrically coupled to one of the second circuits associated with the associated one of the first circuits, each output a skew signal having a duration corresponding to a time period when data on the associated selected ones of the plurality of output pins differs.
In another embodiment of the present invention, a semiconductor device tester is provided having first signal generating means for generating on an output of the first signal generating means an active signal when data on two output pins of a semiconductor device differs and an inactive signal when the data matches and second signal generating means for generating on an output of the second signal generating means an active signal when the data matches and an inactive signal when the data differs. The tester further includes third signal generating means for generating a skew signal corresponding to a time period when the data on the two output pins differs, the third signal generating means being set responsive to the output of the first signal generating means and reset responsive to the output of the second signal generating means.
In another aspect of the present a method is provided in a semiconductor device tester for detecting timing skew between first and second signals on first and second signal lines. The method includes performing a boolean exclusive OR operation on the first and second signals and generating therefrom a skew signal having a duration corresponding to a degree of timing skew between the first and second signals.